Heat extraction is a major bottleneck for microelectronic chips. Advances in silicon micromachining, micro-molding, and material science, such as compound heat sinks with matched coefficient of temperature expansion (CTE), Thermal Interface Materials (TIM), such as thermoplastic, and material growth, such as chemical vapor deposition (CVD) grown carbon nano-tubes and thin film diamond, over the last decade have significantly increased the efficiency and heat extraction ability of micro-cooling systems. However, these technologies are not adequate for wide band gap semiconductors (GaN and SiC) which are generating heat fluxes in excess of 1 kW/cm2 and do not simultaneously address packaging, interconnection and cooling at the wafer-scale.
K-C Chen et al in “Thermal management and novel package design of high power light emitting diodes”, National Cheng Kung University, Taiwan, Electronic Components and Technology Conference, 2008, which is incorporated herein by reference, describe a heat extraction technique; however, the authors do not address the interconnection issue between chips.
A. A. Ali et al in a “Notebook computer with hybrid diamond heat spreader”, Apple Inc, US Patent Application: US 2008/0298021 A1, filed May 31, 2007, which is incorporated herein by reference, describe the use of CVD deposited thin film diamond for a heat spreader. The chip is mounted on thin film diamond using a TIM material (solder, thermal grease, phase change epoxy, or thin film metal: Ti/Pt/Au layer).
R. Feeler et al in “Next-generation microchannel coolers”, Northrop Grumman, Proceedings of SPIE 2008, which is incorporated herein by reference, describe a micro-channel cooler for LED arrays using Low Temperature Co-Fired Ceramic (LTCC) material. They describe using a heat sink made out of AlN, BeO or CVD diamond under the LED chip and then connecting this to the LTCC micro-channel. The CTE of LTCC is close to GaAs and InP so they describe using hard solder, which may be AuSn, to mount the LED on the cooler. The LTTC addresses one major failure mechanism of copper micro-channels, which is their erosion when they are exposed to high water speeds. However, this approach has some disadvantages which include a greater than 300 micron distance between the backside of the chip and the cooling water, which is not optimal, and the fact that LTCC has only a thermal conductivity of 3.5 W/mK compared to the present disclosure which uses aluminum and copper with thermal conductivities of 150 W/mK, and 400 W/mK, respectively. As a result of the low thermal conductivity of LTCC, R. Feeler et al need to use an additional thin film diamond or AlN heat sink under a light emitting diode (LED) chip, and the LED chip mounting requires solder which adds a high thermal resistance layer. R. Feeler et al do not address chip interconnection, which is extremely critical for high frequency applications.
J. Oh et al in “Package-on-package system with heat spreader”, US Published Patent Application 2009/0294941A1, filed May 30, 2008, which is incorporated herein by reference, describe a package-on-package system that includes mounting the chip on a base substrate, positioning an interposer over the chip and forming a heat spreader around the chip and the interposer. Their approach focuses on multi-stacked chips and extracting heat from inside the stack by inserting the heat spreader between the packages as well as at the top of the module. The heat spreader surrounds the entire chip. However this approach has disadvantages. First, it does not offer direct connection to the bottom of the chip, which is the primary area of heat dissipation coming from the active device junction. Instead, heat is removed from the edges of the chip where solder is used to connect the heat sink to the chip, which is a very inefficient way to remove heat and which is definitely inadequate to handle wide band-gap components with high power dissipation. Furthermore, the fact that the heat sink surrounds each chip makes integration of multiple chips difficult since significant component area around each chip is lost. Interconnection between different chips is impossible unless they are combined in a single heat sink, which requires a redesign of the heat sink for each different set of chips.
M. J. Schaenzer et al in “Thermally coupling an integrated heat spreader to a heat sink” US Published Patent Application 2006/0027635 A1, filed Aug. 9, 2004, which is incorporated herein by reference, describe a mounting method where the base of the heat sink is selectively plated with solder and connected to a heat spreader plated with Au. The heat sink is connected to the top of the chip. This approach is close to conventional cooling methods. The disadvantages of this approach are that it requires a high thermal resistance TIM material (solder) to transfer heat from the chip to the heat sink, it can be used for a single chip only and is not applicable to 3D multi-layer systems or multiple chips integrated in a single system, and it offers no solution for interconnecting multiple chips especially for high frequency applications.
More traditional cooling approaches that rely on mounting LED chips on various heat sinks are described in US Published Patent Application US 2009/0134421, filed May 28, 2009, incorporated herein by reference, which describes solid metal block semiconductor light emitting device mounting substrates and packages, US Published Patent Application US 2008/0099770, filed May 1, 2008, incorporated herein by reference, which describes integrated heat spreaders for light emitting devices and related assemblies, US Published Patent Application US 2007/0247851, filed Oct. 25, 2007, incorporated herein by reference, which describes a light emitting diode lighting package with improved heat sink, and US Published Patent Application US 2006/0292747, filed Dec. 28, 2006, incorporated herein by reference, which describes a surface mount power light emitter with integral heat sink.
B. D. Raymond in “Wafer scale integrated thermal heat spreader”, US Published Patent Application US 2009/0108437, filed Oct. 29, 2007, which is incorporated herein by reference, describes a method of creating a heat sink by backside metallization of a wafer. This metallization is realized with composite electroplating of various metallic compounds with variable CTE. Some examples are Cu-Diamond, Cr-Diamond, or metallic compounds with Be, BeO and carbon nano-tubes. After the wafer is backside metalized, the individual chips are diced. The disadvantages of this approach are that it metalizes the entire wafer and it does not offer any methods for structural packaging and interconnecting the chips.
S. Z. Zhao et al in “Flip chip package including a non-planar heat spreader and method of making the same” US Published Patent Application US 2006/0091509, filed Nov. 3, 2004, which is incorporated herein by reference, describe a traditional cooling approach focusing on flip-chip interconnected packages. The main novel concept is the formation of a cavity on the heat sink which allows for easier integration of the chip. The disadvantages of this approach are that it requires special machining of the heat sink and it still needs TIM materials for connecting the chip to the heat sink.
US Published Patent Application US 2008/0128897, filed Jun. 5, 2008, which is incorporated herein by reference, describes a heat spreader for a multi-chip package. Similar to Zhao et al, this approach is a more conventional approach focusing on flip-chip mounted chips, and has disadvantages similar to the Zhao approach.
US Published Patent Application US 2007/0075420, filed Apr. 5, 2007, which is incorporated herein by reference, describes a microelectronic package having direct contact heat spreader and method of manufacturing same. This approach is similar to that described by B. D. Raymond above. The main difference is that the devices are flip-chip mounted active face down to a board and then metalized from the back. Again metallic compounds are proposed for better CTE matching. Compared to the B. D Raymond approach, this approach does offer the advantage of processing known-good-die but it requires flip-chip bonding on a board. This is a reliability concern since the solder bumps and the underfil material used have a high thermal resistance.
Cooling packaging and interconnection method for wide band gap devices are described in U.S. Pat. No. 8,617,927, issued Dec. 31, 2013, U.S. patent application Ser. No. 14/286,923 filed May 23, 2014, A. Margomenos, et al, in “Novel Packaging, Cooling and Interconnection Method for GaN High Performance Power Amplifiers and GaN based RF Front-Ends” European Microwave Conference 2012, and A. Margomenos, et al, “X-Band Highly Efficient GaN Power Amplifier Utilizing Built-In Electroformed Heat Sinks for Advanced Thermal Management”, IEEE International Microwave Symposium 2013, which are incorporated herein by reference. The described approaches rely on selected known good dies for wafer-scale packaging; however, there is no focus on wafer-scale integration.
Hyeog Chan Kwon in U.S. Pat. No. 8,375,576, issued Feb. 19, 2013, which is incorporated herein by reference, describes a method for manufacturing a wafer scale heat slug system including dicing an integrated circuit from a semiconductor wafer, forming a heat slug blank equivalent in size to the semiconductor wafer, dicing the heat slug blank to produce a heat slug equivalent in size to the integrated circuit, attaching the integrated circuit to a substrate, attaching the heat slug to the integrated circuit, and encapsulating the integrated circuit. The disadvantage of this approach is its serial and die-level nature.
What is needed is a low-cost and manufacturable wafer-level integration and processing technology that addresses thermal management limitations in high-power-density active devices such as GaN devices and GaN RF MMIC circuits. The embodiments of the present disclosure address these and other needs.